Malgorzata Marek-Sadowska

Professor

Electrical & Computer Engineering

Malgorzata Marek-Sadowska

Contacts

Department of Electrical and Computer Engineering
University of California
Santa Barbara, CA 93106-9560

tel: (805) 893-2721
fax: (805) 893-3262
mms@ece.ucsb.edu

Research Description

Malgorzata Marek-Sadowska's research interests are in the area of computer-aided design with an emphasis on layout and logic synthesis of VLSI circuits and systems. Her earlier works have dealt with simulation of nonlinear circuits and timing verification.

Research Groups

Biography

From 1976 to 1982 she was Assistant Professor at the Institute of Electron Technology at the Technical University of Warsaw. She was invited to be a Visiting Professor in the Electrical Engineering Department of the University of California at Berkeley from 1979-80. She became a Research Engineer at the Electronics Research Laboratory in 1979 and continued there until 1990, when she joined the Department of Electrical and Computer Engineering at the University of California, Santa Barbara, as a Professor. Professor Marek-Sadowska has been a member of numerous technical committees, including the Technical Committee of the International Conference on Computer Aided Design, the Technical Committee of the Design Automation Conference, and the Technical Committee International Workshop on Placement and Routing. From 1989 to 1993 she was Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and Editor-in-Chief from 1993 to 1995. She has been Associate Editor for the Journal of Circuits, Systems, and Computers since 1990, and serves as a reviewer for numerous technical journals.


Selected Publications

  • A congestion-driven placement framework with local congestion prediction, ACM Great Lakes Symposium on VLSI, 2005, 488-493, Qinghua Liu, Malgorzata Marek-Sadowska
  • An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis, ISQED, 2005, 654-661, Chung-Kuan Tsai, Malgorzata Marek-Sadowska
  • Benefits and Costs of Power-Gating Technique, ICCD, 2005, 559-566, Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif
  • Clock skew bounds estimation under power supply and process variations, ACM Great Lakes Symposium on VLSI, 2005, 332-336, Hailin Jiang, Kai Wang, Malgorzata Marek-Sadowska
  • mFAR: fixed-points-addition-based VLSI placement algorithm, ISPD, 2005, 239-241, Bo Hu, Yue Zeng, Malgorzata Marek-Sadowska
  • Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement, ICCD, 2005, 31-37, Qinghua Liu, Malgorzata Marek-Sadowska
  • Skew-programmable clock design for FPGA and skew-aware placement, FPGA, 2005, 33-40, Chao-Yang Yeh, Malgorzata Marek-Sadowska
  • Wire length prediction-based technology mapping and fanout optimization, ISPD, 2005, 145-151, Qinghua Liu, Malgorzata Marek-Sadowska
  • Buffer sizing for clock power minimization subject to general skew constraints, DAC, 2004, 159-164, Kai Wang, Malgorzata Marek-Sadowska
  • On designing via-configurable cell blocks for regular fabrics, DAC, 2004, 98-203, Yajun Ran, Malgorzata Marek-Sadowska