Biography
Professor Patrick Yue received his B.S. degree in Electrical Engineering with highest honors from the University of Texas at Austin in 1992, and his M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1994 and 1998, respectively. He has over fifteen years of experience in the IC industry and academia. His expertise and research interests include CMOS RF and high-speed IC design, device and passive modeling, and CAD tools for analog design.
Since July 2006, he has been an Associate Professor of the ECE Department at University of California, Santa Barbara. He has also been the Associate Director for the Computer Engineering Program since 2007. From 2003 to 2006, he was an Assistant Professor of the ECE Department at Carnegie Mellon University, Pittsburgh, PA. Before entering academia, he co-founded Atheros Communications (NSDQ: ATHR) in 1998, where he spent four years and was a key member of the team that delivered the world’s first single-chip IEEE 802.11a RF transceiver in standard CMOS. In 2002, he joined another startup, Aeluros (now part of Netlogic, NSDQ: NETL), where he worked on signal integrity and device modeling for 10-Gbps serial link circuits in digital CMOS. While working in the industry, he has held the position of a Consulting Assistant Professor in the Department of Electrical Engineering at Stanford University. In this role, he supervised several Ph.D. candidates on RFIC and device modeling research. Patrick is an active consultant to the IC industry and he currently serves on the advisory boards of several semiconductor startups in the U.S. and mainland China.
Professor Yue has contributed to more than fifty peer-reviewed technical papers and two book chapters. He was the co-recipient of the 2003 International Solid-State Circuits Conference (ISSCC) Best Student Paper Award for demonstrating the first on-chip standing-wave clock distribution circuit. His 1998 paper “On-chip spiral inductors with patterned ground shields for Si-based RF ICs” is among the top cited articles in the history of the IEEE Journal of Solid-State Circuits according Thomson ISI. He currently holds thirteen U.S. patents, most of which are utilized in commercial products. He has served on the technical program committees of the IEEE RFIC Symposium (RFIC), IEEE Asian Solid-State Circuit Conference (A-SSCC), International Symposium on VLSI Design, Automation and test (VLSI-DAT), IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), and IEEE Compound Semiconductor Integrated Circuits Symposium (CSICS). He has been a member of the IEEE Electron Devices Society VLSI Technology and Circuits Committee and a Senior Member of IEEE since 2005.
Awards/Honors
- Best Student Paper, IEEE International Solid-State Circuits Conference (ISSCC), 2003
- All-Time Top Cited Paper in IEEE Journal of Solid-State Circuits (JSSC), 1998
Selected Publications
See complete list of publications
- A two-tone test method for continuous-time adaptive equalizers, Design, Automation and Test in Europe Conference and Exposition (DATE), 2007, 1283-1288, Dongwoo Hong, Shadi Saberi, Kwang-Ting Cheng, C. Patrick Yue
- Low-Power, Parallel Interface with Continuous-Time Adaptive Passive Equalizer and Crosstalk Cancellation, Design of High-Speed Communications Circuits, 2006, 459-476, C.P. Yue, J. Park, R. Sun, L.R. Carley, and F. O’mahony
- Analysis and Synthesis of On-Chip Spiral Inductors, IEEE Transactions on Electron Devices, Vol. 52, No.2, 2005, 176-182, N.A. Talwalkar, C.P. Yue, and S.S. Wong
- Experimental Evidence for Gyromagnetic Damping in Magnetic Heads Determined by Impedance Measurements up to 9 GHz, IEEE Transactions on Magnetics, Vol. 41, No. 10, 2005, 2923-2925, A. Kaya, C.P. Yue, and J.A. Bain
- Scalability of RF CMOS (Invited), IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Digest of Papers, 2005, 53-56, C.P. Yue and S.S. Wong
- Extraction and Applications of On-Chip Interconnect Inductance (Invited), Proceedings of the 7th International Conference on Solid-State and Integrated-Circuit Technology (ICSSICT), 2004, 141-146, S.S. Wong, S.-Y. Kim, C.P. Yue, R. Chang, F. O'Mahony
- Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications, IEEE Journal of Solid-State Circuits, Vol. 39, No. 6, 2004, 863-870, N.A. Talwalkar, C.P. Yue, H. Gan, and S.S. Wong
- Modeling and optimization of substrate resistance for RF-CMOS, IEEE Transactions on Electron Devices, Vol. 51, No.3, 2004, 421-426, R.T. Chang, M.-T. Yang, P.P.C. Ho, Y.-J. Wang, Y.-T. Chia, B.-K. Liew, C.P. Yue, and S.S. Wong
- A 10-GHz Global Clock Distribution Using Coupled Standing-Wave Oscillators, IEEE Journal of Solid-State Circuits, Vol. 38, No. 11, 2003, 1813-1820, F. O'Mahony, C.P. Yue, M.A. Horowitz, S.S. Wong
- Low-Latency Modulated Signaling over On-Chip Electrical Interconnects, IEEE Journal of Solid-State Circuits, Vol.38, No.5, 2003, 834-838, R.T. Chang, N. Talwalkar, C.P. Yue, and S.S. Wong
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