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Forrest BrewerProfessor Electrical & Computer Engineering  ContactsDepartment of Electrical and Computer Engineering tel: (805) 729-1410 |
Research DescriptionVLSI design and coupled tools development based on systematic and formal approaches as well as heuristic analysis. Processor and controller development for embedded, low power and environmentally challenged applications. Interfacing and sampling-based mixed signal design aimed a high loop bandwidth, extreme low power control. Low Power Control: This work started one year ago seeks to drastically reduce the power consumption of digital feedback controller which have become ubiquitous in embedded systems used in cars, appliances and portable phones. The essential issue is that control algorithms perform largely repetitive tasks on data that is usually slowly changing, or changing at rates defined by physically limited systems. All current approaches to these systems rely on general purpose or DSP specific computers, neither of which exploiting this property. These assumptions are particularly pernicious in the case of MEMS (micro mechanical systems). Scaling of the physical size leads to increasing loop bandwidth requirements making the excess power dissipation even greater. Our first efforts in this line were hardware multi-threaded processors which could exploit the bursty nature of control computations. This effort is multi-disciplinary and includes collaborations with Prof. Roy Smith (Controls), Prof. Tim Sherwood (Architecture), and Prof. Kim Turner (Mechanical Engineering). This work has already lead to a major funding request. Fault Tolerance: (EDAC) Work begun two years ago into the issue of local fault tolerance has germinated into a study of circuit efficient design techniques for SER and MER in digital systems. This work is based on a simple Boolean matrix extension property and has led to two publications (one recently submitted) and a pending patent. The technique allows optimal linear code trade-off from TMR to Hamming with constructed designs. In 90nm technology, this allows EDAC faster than memory access with 5% overhead in memory space, these are the fastest and smallest known results. This effort also led to a current patent pending held by UCSB. PBS+/TDL: is a digital system design language based on a notion of latency tolerant structures in which correctnes is conserved for all implementations of the spec -- but preformance is subject to the design decisions. Based loosely on synchronous event languages like Bluespec and on our own PBS+ (regular expression) protocol specification, TDL allows very concise description of digital computing systems -- for example a few pages of TDL create a synthesizable Verilog spec for a multi-threaded AVR processor, which synthesizes to a high performance (400MHz+ in 0.15um) design nearly automatically. We are actively developing elastic clocking for this language to furhter enhance performance and lower the power requirments. Research Groups |
BiographyProfessor Brewer joined the UCSB faculty in 1988, he was formerly a consulting engineer and a senior engineer at Northrop Corp. Advanced Technology Division. His research interests are in VLSI design as well as computer aided design tools and analysis. Recent work is in the development of a family of specialized microprocessors for low-power/ high-performance embedded closed loop control. This work spans mixed signal design at the sensor and actuator interfaces to multi-threaded digital system design in the digital processing parts. By using multi-threading and other architectural tricks, substantial power reduction and performance improvement is possible when compared to commodity DSP processors for this problem. A related issue in this domain is fault tolerance in the controller as such controllers are often deployed in nasty environments such as automobiles or space applications. He also works on formal techniques for design representation and related software tools as well as generic chip feasibility and design analysis which are done on a consulting basis. An example of the formal work is the processor designs above, which are specified in TDL, a very high level language which provides latency tolerance as well as eliminating a large number of critical paths in the resulting core. Selected Publications
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